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? integrated circuits group lh 28 f 16 0 s 5 t - l 70 a fla sh me mor y 16 m ( 2 m b 8 / 1 mb 16 ) (model no.: lh f 16 ka 9 ) spec no.: el 1 2 7 11 2 a issue date: a ugu st 2 9 , 20 0 0 p roduc t s pecific a tions
sharf? lhf16ka9 .- l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). 4 *office electronics l instrumentation and measuring equipment *machine tools l audiovisual equipment l home appliance *communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. +ntrol and safety devices for airplanes, trains, automobiles, and other transportation equipment *mainframe computers l iraff ic control systems @gas leak detectors and automatic cutoff devices orescue and security equipment l other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *aerospace equipment *communications equipment for trunk lines acontrol equipment for the nuclear power industry *medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. rev.1.9
sharp . . . - lhflgka9 1 - contents page page i introduction. ..................................................... 3 1 .l product overview ................................................ 3 2 principles of operation.. .............................. 6 2.1 data protection ................................................... 7 3 bus operation .................................................... 7 3.1 read ................................................................... 7 3.2 o&put disable .................................................... 7 3.3 standby.. ............................................................. 7 3.4 deep power-down .............................................. 7 3.5 read identifier codes operation.. ......... . ............. 8 3.6 query operation .................................................. 8 3.7 write .................................................................... 8 1 command definitions.. ..................................... 8 4.1 read array command.. ..................................... 1 1 4.2 read identifier codes command.. .................... 11 4.3 read status register command.. ..................... 11 4.4 clear status register command.. ..................... 11 4.5 query command, ............................................... 12 4.51 block status register .................................. 12 4.5.2 cfi ciuery identification stiing.. ................... 13 4.5.3 system interface information.. ..................... 13 4.5.4 device geometry definition ......................... 14 4.5.5 scs oem specific extended query table.. 14 4.6 block erase command ...................................... 15 4.7 full chip erase command ................................ 15 4.8 word/byte write command.. ............................. 16 4.9 multi word/byte write command.. .................... 16 4.10 block erase suspend command.. ................... 17 4.11 (multi) word/byte write suspend command ... 17 4.12 set block lock-bit command.. ........................ 18 4.13 clear block lock-bits command.. ................... 18 4.14 sts configuration command ......................... 19 5 design considerations ................................ .30 5.1 three-line output control ................................ .30 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit configuration polling.. ............................................................. .30 5.3 power supply decoupling.. ............................... .30 5.4 v,, trace on printed circuit boards.. ............... .30 5.5 v,,, v,,, rp# transitions.. .............................. .31 5.6 power-up/down protection.. ............................. .31 5.7 power dissipation ............................................. .31 6 electrical specifications.. ........................ .32 6.1 absolute maximum ratings .............................. .32 6.2 operating conditions ........................................ .32 6.2.1 capacitance ................................................ .32 6.2.2 ac input/output test conditions.. ............... .33 6.2.3 dc characteristics.. ..................................... .34 6.2.4 ac characteristics - read-only operations .36 6.2.5 ac characteristics - write operations.. ....... .39 6.2.6 alternative ce#-controlled writes.. ............. .41 6.2.7 reset operations ........................................ .43 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance.. ........................ .44 7 additional information ............................... .45 7.1 ordering information ......................................... .45 rev. 1.9
sharp . - lhflgka9 2 - LH28F160S5T-L70a 1 gm-bit (2mbx8/1 mbxl6) smart 5 flash memory n smart 5 technology - 5v vcc - 5v vpp n common flash interface (cfi) - universal & upgradable interface n enhanced data protection features - absolute protection with vpp=gnd - flexible block locking - erase/write lockout during power transitions i scalable command set (scs) n extended cycling capability - 100,000 block erase cycles i high speed write performance - 3.2 million block erase cycles/chip - 32 bytes x 2 plane page buffer - 2ps/byte write transfer rate n low power management - deep power-down mode n high speed read performance - automatic power savings mode - 70ns(5v*0.25v), 80ns(5v*0.5v) decreases icc in static mode n operating temperature n automated write and erase - 0c to +7o?c - command user interface i enhanced automated suspend options - status register - write suspend to read n industry-standard packaging - block erase suspend to write - 56-lead tsop - block erase suspend to read n etoxrm* v nonvolatile flash n high-density symmetrically-blocked technology architecture l - thirty-two 64k-byte erasable blocks n cmos process (p-type silicon substrate) i sram-compatible write interface i user-configurable x8 or x16 operation n not designed or rated as radiation hardened sharp?s LH28F160S5T-L70a flash memory with smart 5 technology is a high-density, low-cost, nonvolatile, ,ead/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, slmms and memory :ards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F160S5T-L70a offers three levels of protection: absolute protection with v,, at 3nd, selective hardware block locking, or flexible software block locking. these alternatives give designers jltimate control of their code security needs. the LH28F160S5T-L70a is conformed to the flash scalable command set (scs) and the common flash interface cfi) specification which enable universal and upgradable interface, enable the highest system/device data transfer *ates and minimize device and system-level implementation costs. the LH28F160S5T-L70a is manufactured on sharp?s 0.35um etox tm* v process technology. it come in ndustry-standard package: the 56-lead tsop, ideal for board constrained applications. ?etox is a trademark of intel corporation. rev.1.9
sharp . - lhflgka9 3 - 1 introduction this datasheet contains LH28F160S5T-L70a specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 product overview the lh28f160s&t-l70a is a high-performance 16m- bit smart 5 flash memory organized as 2mbx8/1 mbxl6. the 2mb of data is arranged in thirty-two 64k-byte blocks which are individually erasable, lockable, and unlockable in-system. the memory map is shown in figure 3. i smart 5 technology provides a choice of v,, and v,, combinations, as shown in table 1, to meet system performance and power expectations. 5v v,, provides the highest read performance. v,, at 5v eliminates the need for a separate 12v converter, while v,,=5v maximizes erase and write performance. in addition to flexible erase and program voltages, the dedicated v,, pin gives complete data protection when v,+v,,lk. table 1. vcc.and vp, voltage combinations offered by smart 5 technology vcr: voltage vpp voltage 5v 5v i , internal vcc. and vw detection circuitry automatically configures the device for optimized read and writeoperations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. a block erase operation erases one of the device?s 64k-byte blocks typically within 0.34s (5v voo, 5v v,,) independent of other blocks. each block can be independently erased 100,000 times (3.2 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. a word/byte write is performed in byte increments typically within 9.24us (5v vcc, 5v vpp). a multi word/byte write has high speed write performance of 2uslbyte (5v vcc, 5v v,,). (multi) word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. individual block locking uses a combination of bit: and wp#, thirty-two block lock-bits, to lock ant unlock blocks. block lock-bits gate block erase, ful chip erase and (multi) word/byte write operations block lock-bit configuration operations (set bloce lock-bit and clear block lock-bits commands) se and cleared block lock-bits. the status register indicates when the wsm?s block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. the sts output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using sts minimizes both cpu overhead and system power consumption. sts pin can be configured to different states using the configuration command. the sts pin defaults tc ry/by# operation. when low, sts indicates that the wsm is performing a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. sts-high z indicates that the wsm is ready for a new command, block erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down mode. the other 3 alternate configurations are all pulse mode for use as a system interrupt. the access time is 70ns (tavqv) over the commercial temperature range (0% to +7o?c) and vc, supply voltage range of 4.75v-5.25v. at lower voc voltage, the access time is 80ns (45v-55v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps m-ode, the typical lccr current is 1 ma at 5v v,,. when either ce,# or ce,#, and rp# pins are at vcc, the i,, cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphav) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (tphel) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 56-lead tsop (thin small outline package, 1.2 mm thick). pinout is shown in figure 2. 1 i rev. 1.9
sharp lhflgka9 4 ce# wew oe# rp# wp# sts vw +l kc +- gnd figure 1. block diagram 6 ?7 8 9 10 11 12 13 14 vpp 15 rp# 16 ail 17 40 18 2 20 19 gnd 21 a7 22 % 23 a5 24 2 25 26 a2 al iz: 56 lead tsop standard pinout 14mm x 20mm top view 56 55 wp# we# 54 oe# 53 sts 52 dqts 51 dc27 50 b da;, 49 48 47 46 45 44 dq, 43 vcc 42 gnd 41 b dqii 40 39 :::. 38 dq2 37 vcc 36 35 ei: 34 dq, 33 dqo 32 43 31 byte# 30 nc 29 nc figure 2. tsop 56-lead pinout (normal bend) j rev. 1.9
shari= - lhflgka9 _ - 5 r symbol *o-*20 xjo-dq, ce,#, ce,# rp# oe# we# sts wp# byte# ?pp ?cc gnd nc type input input/ output input input input input open drain output input input supply supply supply table 2. pin descriptions name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. ao: byte select address. not used in x16 mode(can be floated). ai-ak column address. selects 1 of 16 bit lines. as-at!% row address. selects 1 of 2048 word lines. a16420 : block address. data input/outputs: dqo-dc&inputs data and commands during cui write cycles; outputs data during memory array, status register, query, and identifier code read cycles. data pins float to high- impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dqs-dq15:lnputs data during cui write cycles in x16 mode; outputs data during memory array read cycles in xl 6 mode; not used for status register, query and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(byte#=v,, ). data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers decoders, and sense amplifiers. either ceo# or ce,# vih deselects the device and reduces power consumption to standby levels. both cen# and ce,# must be vii to select the devices. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp# vi, enables normal operation. when driven v,,, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. output enable: gates the device?s outputs during a read cycle. write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. sts (ry/by#): indicates the status of the internal wsm. when configured in level mode (default mode), it acts as a ry/by# pin. when low, the wsm is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). sts high z indicates that the wsm is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. for alternate configurations of the status pin, see the configuration command. write protect: master control for block locking. when vi,, locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. byte enable: byte# v,, places device in x8 mode. all data is then input or output on dqo-,, and dq8-t5 float. byte# v,, places the device in x16 mode , and turns off the ac input buffer. block erase, full chip erase, (multi) word/byte write. block lock- bit configuration power supply: for erasing array blocks, writing bytes or configuring block lock-bits. with vpp shal?l= - lhf16ka9 6 . - 2 principles &operation the LH28F160S5T-L70a flash memory includes an on-chip wsm to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status bgister, query structure and identifier codes can be accessed through the cui independent of the vp, voltage. high voltage on vp, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. all functions associated with altering memory contents--block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes-are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, full chip erase, (multi) word/byte write and block lock- bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and mar ining 91 of data. addresses and data are internally atch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to *cad or write data from any other block. write suspend allows system software to suspend a (multi) nerd/byte write to read data from any other flash nemory array location. figure 3. memory map - rev. 1.9
shari= . . lhf16ka9 7 i 2.1 data protection 3.2 output disable depending on the application, the system designer may choose to make the v,, power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to v,,,,. the device accommodates either design practice and encourages optimization of the processor-memory interface. when vpp~vpplk, memory contents cannot be altered. the cui, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage ,is applied to v,,. all write functions are disabled when v,, is below the write lockout voltage vlko or when rp# is at v,,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations. 3 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, query structure;gr status register independent of the v,, voltyge. rp# must be at v,,. the first task is to write the appropriate read mode command (read array, read identifier codes, query or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. five control pins dictate the data flow in and out of the component: ce# (ceo#, ce,#), oe#, we#, rp# and wp#. ce,#, ce,# and oe# must be driven active to obtain data at the outputs. ce,#, ce,# is ihe device selection control, and when active enables the selected memory device. oe# is the data output (dqo-dq,,) control and when active drives the selected memory data onto the i/o bus. we# and sp# must be at vi,. figure 17, 18 illustrates a read :ycle. with oe# at a logic-high level (vi,), the device outputs are disabled. output pins dqo-dq,, are placed in a high-impedance state. 3.3 standby either ce,# or ce,# at a logic-high level (v,,) place: the device in standby mode which substantial! reduces device power consumption. dqo-dq, outputs are placed in a high-impedance state independent of oe#. if deselected during bloc1 erase, full chip erase, (multi) word/byte write am block lock-bit configuration, the device continue: functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v,, initiates the deep power-down mode. in read modes, rp#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. rp# must be held low fo a minimum of 100 ns. time tphqv is required afte, return from power-down until initial memory access outputs are valid. after this wake-up interval, norma operation is restored. the cui is reset to read arra) mode and status register is set to 80h. during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, rp#-ion will abort the operation. sts remains low until the reset operation is complete. memory contents beins altered are no longer valid; the data may be partiali] erased or written. time t,,,, is required after rp#i goes to logic-high (v,,) before another command car be written. as with any automated device, it is important tc a$sert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bii configuration. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1.9
sharp lhflgka9 a -- 3.5 read identifier codes operation 3.6 query operation the read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. the query operation outputs the query structure query database is stored in the 48byte rom. quer) structure allows system software to gain critica information for controlling the flash component query structure are always presented on the lowest. order data output (dqo-dq,) only. 3.7 write ,. : ,.. ::. . . . . . .:. : : : &&tied f& . . : 4 :j / -.ftiu~etmpiementaiion ., ,: lfoc&? lfocq5 -ir.i-i----------------------------- if0004 block 31 status code ,fooo3 :;-----_------------- ----- - ---- -- reserved for ; ,fo(jj(; ?. future lmplemehation : ieffff; : . : .? .? bfock.41; i : : 020000~ : (blq&s 2thrtigh 3?i,) ., . . . ?.? : ; ) ,; olffff.1. : :,: .? resewed?for ., ftiuie iinpteb3ntation ? .? .*. 01~ i : i,..\ ----l ---^ l *----------------- .l --------- 01ooo5 ,,, 010004 block 1 status dode o,ooo3 t---------------------------------- . . ., .. i&serve&for .~ future. i-nylemg&ftion. i. : ., o,m;..?,. .; ,j. .blqckl~ ooffff :. . . . : : ; : reserved for future implement&ion c4)0(& -___ -_--___-- -___ -_-_----_----_----___ ooooo5 omoo4 block 0 status code 000003 000002 device code _------------------------------------- oooool manufacturer code block 0 1 writing commands to the cui enable reading 01 device data and identifier codes. they also contra, inspection and clearing of the status register. when vcc=vcc1,2 and vpp=vpph1, the cui additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the word/byte write command requires the command and address of the location to be written. set block lock-bit command requires the command and block address within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 19 and 20 illustrate we# and ce#-controlled write operations. 4 command definitions when the vp, voltage i v,,,,, read operations from the status register, identifier codes, query, or blocks are enabled. placing vp,+, on v,, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. : figure 4. device identifier code memory map rev. 1.9
shari= lhflgka9 9 . - -- table 3. bus operations(byte#=v,,) mode 1 notes 1 rp# 1 ced 1 ced 1 oe# i we# i address 1 vp,, i dq,,,li i sts read output disable 1 1 r&3,9 1 vlh i vii i vii i vii ! vih ! x 1 x b-ml x 3 v,,-, v,, v,, v,,-, v,h x x high z x vi, vi, standby 3 vi, $h vi, x x x x high z x ii v,h deep power-down 4 v,, x x x x x x high z high z read identifier codes 9 vi, vi, vi, vi, vlh see figure 4 ? note 5 high z query 9 vlh vi, vi, vi, vlh see table x 7-11 note 6 high z write 3,7,&g v,h v,, v,, v,h v,, x x d,n x table 3.1. bus operations(byte#=v , ) mode notes rp# cen# ce,# oe# we# address vp,, dq&, sts read . 1,2,3,9 v,,, v,, v,, v,, v,,, x x dolit x outputbisable 3 v,m v,, v,, v,,-j v,h x x highz x vi, vlh standby 3 vlh vlh vi, x x x x high z x v,, v,,, deep power-down 4 v,, x x x x x x high z high z read identifier codes 9 ?1, yl yl yl ?1, see figure 4 ? note 5 high z query 9 vi, vi, vi, vi, vlh see table x 7-11 note 6 high z write 3,7,&g v,h v,, v,, v,,, v,, x x d,n x notes: 1. refer to dc characteristics. when vpplvpplk, memory contents can be read, but not altered. 2. x can be vil or v,h for control pins and addresses, and vp,,, or vp,,+, for v,,. see dc characteristics for vp,,, and vp,,, voltages. 3. sts is vol (if configured to ry/by# mode) when the wsm is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. it isfloated during when the wsm is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power;down mode. 4. rp# at gndlt0.2v ensures the lowest deep power-down current. 5. see section 4.2 for read identifier code data. 6. see section 4.5 for query data. 7. command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when vpp=vpr+,1 and vcc=vcc,,2. 8. refer to table 4 for valid d,, during a write operation. 9. don?t use the timing both oe# and we# are vi,. rev. 1.9
sham= k 1 2 3 4 5 6 7 a 9 11 _- lhflgka9 10 _ - - command read array/reset read identifier codes table 4. command definition@) bus cycles notes first bus cycle second bus cycle req?d oper(?) addr(*) data(?) ope#) addr(*) data@) 1 write x ffh 22 4 write x 90h read ia id level-mode for erase and write 2 1 write 1 x 1 b8h 1 write 1 x 1 ooh (ry/by# mode) sts configuration pulse-mode for erase sts confiauration write write write t x 1 b8h x i b8h x b8h write write olh 02h 03h x t3 x x pulse-mod< for write sts configuration pulse-mode for erase and write dotes: . bus operations are defined in table 3 and table 3.1. i. x=any valid address within the device. la=ldentifief. code address: see figure 4. qa=query offset address. ba=address within the block being erased or locked. wa=address of memory location to be written. ?. srd=data read from status register. see table 14 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. qd=data read from query database. . following the read identifier codes command, read operations access manufacturer, device and block status codes. see section 4.2 for read identifier code data. . if the block is locked, wp# must be at vi, to enable block erase or (multi) word/byte write operations. attempts to issue a block erase or (multi) word/byte write to a locked block while rp# is v,,. . either 40h or 10h are recognized by the wsm as the byte write setup. . a block lock-bit can be set while wp# is vi,. . wp# must be at vi, to clear block lock-bits. the clear block lock-bits operation simultaneously clears nil hlnck lock-bits. . following the third bus cycle, inputs the write address and write data of ?n? times. finally, input the confirm command ?doh?. 0. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 1.9
sharp lhf16ka9 11 . - - - 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend and (multi) word/byte write suspend command. the read array command functions independently of the v,, voltage and rp# must be vi,. 4.2 &ad identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the :ommand write, read cycles from addresses shown in =igure 4 retrieve the manufacturer, device, block lock zonfiguration and block erase status (see table 5 for dentifier code values). to terminate the operation, nrite another valid command. like the read array zommand, the read identifier codes command ?unctions independently of the v,, voltage and rp# nust be vi,. following the read identifier codes :ommand, the following information can be read: table 5. identifier codes code 1 address 1 data 1 *block is unlocked dc&,=0 *block is locked dc&= 1 l last erase operation completed successfully dq, =0 *last erase operation did not completed successfully dc+1 *reserved for future use dq2-, mote: 1. x selects the specific block status code to be read. see figure 4 for the device identifier code memory map. 4.3 read status register command the status register may be read to determine when 2 block erase, full chip erase, (multi) word/byte write oi block lock-bit configuration is complete and whethel the operation completed successfully(see table 14) it may be read at any time by writing the read statu: register command. after writing this command, al subsequent read operations output data from the status register until another valid command is written the status register contents are latched on the falling edge of oe# or ce#(either ce,# or ce,#), whichever occurs. oe# or ce#(either ceo# or ce,#; must toggle to vi, before further reads to update the status register latch. the read status register command functions independently of the v,, voltage. rp# must be vi,. the extended status register may be read tc determine multi word/byte write availability(see table 14.1). the extended status register may be read al any time by writing the multi word/byte write command. after writing this command, all subsequeni read operations output data from the extended status register, until another valid command is written. multi word/byte write command must be re-issued to update the extended status register latch. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 and sr.1 are set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 14). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurs during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v,, voltage. rp# must be v,,. this command is not functional during block erase, full chip erase, (multi) word/byte write block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes. rev. 1.9
shari= lhf16ka9 12 i 4.5 query command query database can be read by writing query command (98h). following the command write, read cycle from address shown in table 7-l 1 retrieve the critical information to write, erase and otherwise control the flash component. ac of query offset address is ignored when x8 mode (byte#=v,,). query data are always presented on the low-byte data output (dc&,-dq,). in x16 mode, high-byte :dqs-dq,,) outputs ooh. the bytes not assigned to xty information or reserved for future use are set to ?0?. this command functions independently of the l/p,, voltage. rp# must be v,,. 1 table 6. example of query structure output mode 1 offset address 1 oute nit dq,c;-j-, dq,-, a,, a,, a,, a,, a,, a, 1 , 0 , 0 , 0 , 0 , 0 (20h) high z "q" x8 mode 1 , 0 , 0 , 0 , 0 , 1 (21h) high z "q" 1, o,o,o,l ,0(22h) highz "i?" 1 , 0 , 0 , 0 , 1 , 1 (23h) high z "fl" a,, a,, a,, a,, a, x16mode 1 ,o,o,o,o (10h) ooh "q" 1 ,o,o,o,l (11h) ooh "r" -1 1.5.1 block status register rhis field provides lock configuration and erase status for the specified block. these informations are only available when device is ready (sr.7=1). if block erase or full chip erase operation is finished irregulary, block erase status iit will be set to ?1?. if bit 1 is ?l?, this block is invalid. offset (word address) (ba+2)h table 7. query block status register length description olh block status register bit0 block lock configuration o=block is unlocked 1 =block is locked bit1 block erase status o=last erase operation completed successfully mote: ./ , 1 =last erase operation not completed successfully bit2-7 reserved for future use 1. ba=the beginning of a-block address. rev. 1.9
sharp lhflgka9 13 4.5.2 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported. table 8. cfi query identification string description 13h,14h 15h,16h 17h,18h 02h 02h 02h primary vendor command set and control interface id code 01 h,ooh (scs id code) address for primary algorithm extended query table 31 h,ooh (scs extended query table offset) alternate vendor command set and control interface id code ooooh (ooooh means that no alternate exists) address for alternate algorithm extended query table ooooh (ooooh means that no alternate exists) 4.5.3 system interface information the following device information can be useful in optimizing system interface software. \ i 1fh .olh 20h olh 21h olh 22h olh 23h 01h 24h olh 25h olh 26h olh table 9. system information string description v,, logic supply minimum write/erase voltage 27h 12.7v) vcc logic supply maximum write/erase voltage 55h (5.5v) v,, programming supply minimum-write/erase voltage 27h (2.7v) vpp programming supply maximum write/erase voltage 55h (5.5v) typical timeout per single byte/word write 03h (23=8us) typical timeout for maximum size buffer write (32 bytes) 06h (26=64us) typical timeout per individual block erase oah (oah=lo, 210=1024ms)- typical timeout for full chip erase ofh (ofh=15, 215=32768ms) maximum timeout per single byte/word write, 2n times of typical. 04h (24=1 6, 8usxl6=128us) maximum timeout maximum size buffer write, 2n times of typical. 04h (24=1 6, 64usxl6=1024us) maximum timeout per individual block erase, 2n times of typical. 04h (24=1 6, 1024msxl6=16384ms) maximum timeout for full chip erase, 2n times of typical. 04h (24=1 6,32768msxl6=524288ms) rev. 1.9
shari= lhf16ka9 -- 1.5.4 device geometry definition rhis field provides critical details of the flash device geometry. offset (word address) 27h 28h,29h 2ah,2bh 2ch 2dh,2eh i 2fh,30h table 10. device geometry definition length description 01h device size 15h (15h=21, 221=2097152=2m bytes) 02h flash device interface description 02h,ooh (x8/x1 6 supports x8 and xl 6 via byte#) 02h maximum number of bytes in multi word/byte write 05h,ooh (25=32 bytes ) olh number of erase block regions within device 01 h (symmetrically blocked) 02h the number of erase blocks 1 fh,ooh (1 fh=31 ==> 31+1=32 blocks) 02h the number of ?256 bytes? cluster in a erase block ooh,ol h (olooh=256 ==>256 bytes x 256= 64k bytes in a erase block) $55 scs oem specific extended query table zertain flash features and commands may be optional in a vendor-specific algorithm specification. the optional rendor-specific query table(s) may be used to specify this and other types of information. these structures are defined solely by the flash vendor(s). table 11. scs oem specific extended query table offset (word address) length description 31 h,32h,33h 03h pri 50h,52h,49h 34h olh 31 h (1) major version number , ascii 35h olh 30h (0) minor version number, ascii 36h,37h, 04h 38h,39h ? qfh,ooh,ooh,ooh optional command support bito=l : chip erase supported bitl=l : suspend erase supported bit2=1 : suspend write supported bit3=1 : lock/unlock supported bit4=0 : queued erase not supported bit5-31 =o : reserved for-future use 3ah olh olh supported functions after suspend bito=l : write supported after erase suspend bit1 -7=o : reserved for future use 3bh,3ch 02h 03h,ooh block status register mask bito=l : block status register lock bit [bsr.o] active bitl=l : block status register valid bit [bsr.l] active bit2-l5=0 : reserved for future use 3dh olh vcc logic supply optimum write/erase voltage(highest performance) 50h(5.ov) 3eh olh vpp programming supply optimum write/erase voltage(highest performance) 50h@ov) 3fh reserved reserved for future versions of the scs specification rev. 1.9
sharp ..~ lhflgka9 15 4.6 block erase command block erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the sts pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sk5 being set to ?1 ?i. also, reliable block erasure san only occur when vcc=vcc1,2 and vpp=vpph,. in the absence of this high voltage, block contents are orotected against erasure. if block erase is attempted while v&l,,,,, sr.3 and sr.5 will be set to ?1 ?i. successful block erase requires that the :orresponding block lock-bit be cleared or if set, that tip#=v,,. if flock erase is attempted when the :orrespondincj? block lock-bit is set and wp#=v,,, sr.l and sr.5 will be set.to ?1?. erase setup is first written, followed by a full chil erase confirm. after a confirm command is written device erases the all unlocked blocks from block 0 tc block 31 block by block. this command sequenct requires appropriate sequencing. bloc1 preconditioning, erase and verify are handle< internally by the wsm (invisible to the system). afte the two-cycle full chip erase sequence is written, thf device automatically outputs status register da& when read (see figure 6). the cpu can detect ful chip erase completion by analyzing the output data o the sts pin or status register bit sr.7. when the full chip erase is complete, status registe; bit sr.5 should be checked. if erase error i: detected, the status register should be cleared before system software attempts corrective actions. the cu remains in read status register mode until a ne\n command is issued. if error is detected on a bloce during full chip erase operation, wsm stops erasing reading the block valid status by issuing read ic codes command or query command informs whict blocks failed to its erase. this two-step command sequence of set-up followec by execution ensures that block contents are no? accidentally erased. an invalid full chip erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1?. also, reliable ful chip erasure can only occur when vcc=vcc,,2 ant vpp=vpphi. in the absence of this high voltage, block contents are protected against erasure. if full chip erase is attempted while v,,iv,,,,, sr.3 and sr.5 will be set to ?1?. when wp#=v,,, all blocks are erased. independent of block lock-bits status. when wp#=v,,, only unlocked blocks are erased. in this case, sr.l and sr.5 will not be set to ?1?. full chip erase can not be suspended. i )i r 4.7 full chip erase command rhis command followed by a confirm command :doh) erases all of the unlocked blocks. a full chip rev. 1.9
sharp ; lhflgka9 . - 16 4.8 word/byte write command word/byte write is executed by a two-cycle command sequence. word/byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word/byte write and write verify algorithms internally. after the word/byte write sequence is written, the device automatically outputs status register data when read (see figure 7). the cpu can detect the completion of the word/byte write event by analyzing the sts pin or status register bit sr.7. when word/byte write is complete, status register bit sr.4 should be checked. if word/byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for ?1?s that do not successfully write to ?0?s. the cui remains in read status register mode until it receives another command. reliable word/byte writes can only occur when vcc=vcc,,2 and vpp=vpph1. in the absence of this high voltage, memory contents are protected against word/byte writes. if word/byte write is attempted while v,,&v,,,,, status register bits sr.3 and sr.4 will be set to ?1?. successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that wp#=v,,. if word/byte write is attempted when the corresponding block lock-bit is set and wp#=v,l, sr.l and sr.4 will be set to ?1?. word/byte write operations with v,,LH28F160S5T-L70a has two buffers. if an error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. status register bit sr.4 will be set to ?1 ?i. no multi word/byte write command is available if either sr.4 or sr.5 are sei to ?1?. sr.4 and sr.5 should be cleared before issuing multi word/byte write command. if a multi word/byte write command is attempted past an erase block boundary, the device will write the data to flash array up. to an erase block boundary and then stop writing. status register bits sr.4 and sr.5 will be se1 to ?1 ?i. reliable multi byte writes can only occur when vcc=vcc1,2 and vpp=vpphi. in the absence of this high voltage, memory contents are protected against multi word/byte writes. if multi word/byte write is attempted while v,+v,,,k, status register bits sr.3 and sr.4 will be set to ?1?. successful multi word/byte write requires that the corresponding block lock-bit be cleared or, if set, that wp#=v,,. if multi byte write is attempted when the corresponding block lock-bit is set and wp#=v,l, sr.l and sr.4 will be set to ?1 i?. rev. 1.9
sharp lhflgka9 17 . - - 1.10 block erase suspend command the block erase suspend command allows block- erase interruption to read or (multi) word/byte-write data in another block of memory. once the block- xase process starts, writing the block erase suspend command requests that the wsm suspend :he block erase sequence at a predetermined point in :he algorithm. the device outputs status register data ,vhen read after the block erase suspend command s written. polling status register bits sr.7 and sr.6 xn determine when the block erase operation has deen suspended (both will be set to ?1?). sts will also transition to high z. specification twhrh2 defines :he block erase suspend latency. at this qoint, a read array command can be written to read data from blocks other than that which is suspended. a (multi) word/byte write command sequence can also be issued during erase suspend to program data in other blocks. using the (multi) word/byte write suspend command (see section 4.1 l), a (multi) word/byte write operation can also be suspended. during a (multi) word/byte write operation with block erase suspended, status register bit sr.7 will return to ?0? and the sts (if set to ry/by#) dutput will transition to vol. however, sr.6 will remain ?1? to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm inrill continue the block erase process. status register oits sr.6 and sr.7 will automatica!ly clear and sts nil1 return to v&. after the erase resume command is written, the device automatically outputs status register data when read ?(see figure 10). v,, must remain at vpph1 (the same v,, level used for block erase) while block erase is suspended. rp# must also remain at vi,. block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed. 4.11 (multi) word/byte write suspend command the (multi) word/byte write suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. once the (multi) word/byte write process starts, writing the (multi) word/byte write suspend command requests that the wsm suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the (multi) word/byte write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to ?1?). sts will also transition to high z. specification twhrhl defines the (multi) word/byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while (multi) word/byte write is suspended are read status register and (multi) word/byte write resume. after (multi) word/byte write resume command is written to the flash memory, the wsm will continue the (multi) word/byte write process. status register bits sr.2 and sr.7 will automatically clear and sts will return to v,,. after the (multi) word/byte write command is written, the device automatically outputs status register data when read (see figure 11). v,, must remain at v,,,, (the same v,, level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. wp# must also remain at v,, or yl* rev. 1.9
sharp lhflgka9 . - 18 4.12 set block lock-bit command a flexible block locking and unlocking scheme is enabled via block lock-bits. the block lock-bits gate program and erase operations with wp#=v,,, individual block lock-bits can be set using the set block lock-bit command. see table 13 for a summary of hardware and software write protection options. set block lock-bit is executed by a two-cycle command sequence. the set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set block lock-bit algorithp. after the sequence is written, the device automatically outputs status register data when read (see figure 12). the cpu can detect the completion of the set block lock-bit event by analyzing the sts pin output or status register bit sr.7. when the set block lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to ?1?. also, reliable operations occur only when vcc=vccv2 and vpp=vpphi. in the absence of this high voltage, block* lock-bit contents are protected against alteration. a successful set block ?lock-bit operation requires wp#=v,,. if it is attempted with wp#=v,,, sr.l and sr.4 will be set to ?1? and the operation will fail. set block lock-bit operations with wp# sharp lhflgka9 4.14 sts configuration command the status (sts) pin can be configured to different states using the sts configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or rp# is set to v,,. upon initial device power-up and after exit from deep power-down mode, the sts pin defaults to ry/by# operation where sts low indicates that the wsm is busy. sts high z indicates that the wsm is ready for a new operation. table 12. sts configuration coding description configuration bits effects set sts pin to default level mode ooh (ry/by#). ry/by# in the default level-mode of operation will indicate ~ wsm status condition. set sts pin to pulsed output signal for specific erase operation. in this olh mode, sts provides low pulse at the completion of block erase, full chip erase and clear block lock-bits operations. to reconfigure the sts pin to other modes, the sts configuration is issued followed by the appropriate configuration code. the three alternate configurations are all pulse mode for use as a system interrupt. the sts configuration command functions independently 02h set sts pin to pulsed output signal for a specific write operation. in this mode, sts provides low pulse at the completion of (multi) byte write and set block lock-bit operation. of the vpp voltage and rp# must be vi,+. set sts pin to pulsed output signal for specific write and erase 03h operation. sts provides low pulse at the completion of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. table 13. write protection alternatives operation block lock-bit wp# effect block erase, . 0 vi, or vi,., block erase and (multi) word/byte write enabled (multi) word/byte , write vi, block is locked. block erase and (multi) word/byte write disabled ./ , vi, block lock-bit override. block erase and (multi) word/byte write enabled full chip erase 091 v,, all unlocked blocks are erased, locked blocks are not erased x vp , all blocks are erased set block lock-bit x v,, set block lock-bit disabled v,h set block lock-bit enabled clear block lock-bits x v,, clear block lock-bits disabled v,w clear block lock-bits enabled rev. 1.9
sharp lhflgka9 20 _ - .- table 14. status register definition wsms j bess 1 ecblbs 1 wsblbs 1 vpps i wss dps r 7 6 5 4 3 2 1 0 notes: sr.7 = write state machine status 1 = ready 0 = busy sr.6 = block erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear block lock-bits status 1 = error in erase or clear bloc1 lock-bits check sts or sr.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. sr.6-0 are invalid while sr.7=?0?. if both sr.5 and sr.4 are ?1?s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or sts configuration attempt, an improper command sequence was entered. 0 = successful erase or clear block lock-bits sr.3 does not provide a continuous indication of v,, 4 level. the wsm interrogates and indicates the v,, level sr.4 = write and set block lock-bit status only after block erase, full chip erase, (multi) word/byte 1 = error in write or set block lock-bit write or block lock-bit configuration command 0 = successful write or set block lock-bit sequences. sr.3 is not guaranteed to reports accurate sr.3 = v,, status feedback only when v,p&/,p,, . 1 = v,, low detect, operation abort o=v,,ok sr.l does not provide a continuous indication of block lock-bit values. the wsm interrogates block lock-bit, sr.2 = write suspend status 1 = write suspended 0 = write in progress/completed and wp# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set and/or sr.l = device protect status wp# is not v,,. reading the block lock configuration 1 = block lock-bit and/or wp# lock detected, codes after writing the read identifier codes command indicates block lock-bit status. operation abort 0 = unlock - sr.0 is reserved for future use and should be masked sr.0 = reserved for future*enhancements out when polling the status register. table 14.1. extended status register definition sms r r r r r r r 7 6 5 4 3 2 1 0 notes: xsr.7 = state machine status 1 = multi word/byte write available after issue a multi word/byte write command: xsr.7 0 = multi word/byte write not available indicates that a next multi word/byte write command is available. xsr.g-o=reserved for future enhancements xsr.g-0 is reserved for future use and should be masked out when polling the extended status register. rev. 1.9
sharp block address check if desired full status check procedure (c) dewce protect error ~. lhfigkas 21 . - bus opowlotl commrnd comments write read standby read status rsgister data-70h addr-x status ragistar data check sr.7 l-wsm ready (bwsm busy write etaso setup data&uh adds-within block to be erased writ.3 erase confirm data-doh adds-within block to be erased read standby status register data check sr.7 1 -wsm ready o=wsm busy repeat for subsequent block erasures. full status check can be dona after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read away mode. bus operalion standby comma?d comments check sr.3 lxvpp error detect check sr. 1 standby i-device protect detect wp#~vil,blo& lock-bit is set only required for systems implementing lock-bit configuration standby standby check sr.4.5 soti l=command sequence enw check sr.5 l=elock erase error %t.5,sr.4,sr.3 and sr.1 are onb cleared by the clear status register command in causes where multiple blocks are emsed before full status is checked. f error is detected. clear the status register before attempting ratly or other error raco?wy. figure 5. automated block erase flowchart l- rev. 1.9
sharf= lhf16ka9 . - 22 i -- check if desired full status check procedure read status register data(sae above) full chip erase successful read status register data i :uii stabs check can be done after each full chip erase. wit0 ffh after tie last opera(ion to place device in mad array mode. / o:~c? 1 grnrnmd / comments standby check sr.3 l=vpp error detect standby chedc sr.4.5 both l=command sequence error check sr.5 l-full chip erase error sr.s.sr.4.sr.3 and sr.1 are only dewed by the clear status register command in cases where multiple blocks are erased before full status is chedwd. if error is detected. clear the status register before attempting retry or other error ?-eccnery. j figure 6. automated full chip erase flowchart rev. 1.9
shari= c- stall \ 0 0 sr.7= , full status check procedure (5zyttz?] . . . , device protect enw lhfigkas 23 _ - .i command comments write read standby read status register data-70h add,=x status register data check sr.7 l-w% ready oiwsm busy wlite write setup word/byte wlite word/byte write datw4oh or 10h addr-locabon to be written data-data to be written addr-location to be written read status register data standby check sr.7 1 =wsm reacfy o.wsm busy repeat for subsequent word/byte writes. sr full stah~s check can be done after each worn write. or after a sequence of wordbyte writes. write ffh after the last wotdibyte write operabn to place device in mad anay mode. bus op~tion command comments standby check sr.3 l.vpp error detect check sr.1 standby i-devise pmtect detect wpy-v#o& lock-bit is set only required for systems implementing lock-bit configuration standby check sr.4 l-data write error sr.4,sr.3 and sr.1 are only dearud by the clear status register command in cases where multiple locations are witten before full status is checked. if em)r is detected, clear the status regster before attempting retry or other error recovery. figure 7. automated word/byte write flowchart rev. 1.9
lhflgka9 24 _ - l- 4 write buffer data, start address write buffer data, \ abort device address wlite doh i read status register i r bus opsration command t write stip multi wordbyte write read standby write (n&l) write (n&2,3) read -i----- standby comments datapebh add&tart address extended status register data check xsr.7 l-multi word/byte write ready o-multi woldmyte writ0 buoy data-word or byte count (n)-1 addr-start address datapbuffer data add&tart address data-buffer data addr-device address data-doh addr=x status register data check sr.7 1 =wsm ready 0s.wsm busy 1, byte or word count values on dc!,,., are loaded into the count register. 2. write buffer contents will be programmed at the start address. 3. align the start address on a write buffer boundary for maximum programming perfonance. 4.the device aborts the multi word/byte write command if the current address is outside of theprfginal block address. b.the status register indicates an ?improper command sequence? if the multi wordbyte command is aborted. follow this with a clear status register command. sr full status check can be done after each multi wov9byte write, or after q sequence of multi wotiyte writes. write ffh after the last multi wordbyte write operation to place device in read array mode. figure 8. automated multi word/byte write flowchart rev. 1.9
sharp lhfigkas fullstatuscheckprocewre for multi word/byte write operation read status register command comments check sr.3 t=vpp ermr detect device protect enor stsndby standby check sr.1 l=dovlce protect detect wpwpv,l,bfock lock-bit is set only mquimd for systems implementing lock-bit contigumtion check sft.4.5 both 1gommand sequence error standby check sr.4 l-data write ermr srs.sr.4.sr.3 and sr.1 are only deamd by the clear status register command in casas where multiple locations are written before full status is dmcked. if ermr is detected. clear the status register before attempting retry orouw error recovery. figure 9. full status check procedure for automated multi word/byte write rev. 1.9
sharp standby check sr.7 1 -wsm ready onwsm bury sr.7= 0 chock sr.6 standby l-block erase suspended 1 o-block erase completed data&oh write etwe resulls addr-x (multi) wofd/byte write loop bus opemioll command comments *- lhflgka9 26 _ - -- i i figure 10. block erase suspend/resume flowchart rev. 1.9
sharp ,*, i i i +- sr.7- 0 1 write ffh read army data (mulli) worvsvto write\ compk ied / (multi) wodsyte write data&h suspend addhx read status register data addr=x chock sr.7 l-wsm ready 0a.ws.m busy standby chech 533.2 b(mul6) word?eyte write suspended o-(multi) word/byte write completed datarffh write addhx read array locatbns other than that being written. .- lhflgka9 _ - 27 .i write (multi) word/byte write data-doh resume addr-x figure 11. (multi) word/byte write suspend/resume flowchart rev. 1.9
sharp .- lhflgka9 _ - block address block address 0 + sr.7= 4 1 check if desired full status check procedure (t) command i writ.3 set block lock-bit setup data-6ol-l add&lock address repeat for subsequent block lock-bit set operations. full status chsck can be done after each block l&-bit set operation or after a sequence of block lock-bit set operations. write ffh after the last block lo&-bit set operation to place device in read army mode. command comments i standby check sr.3 i-vpp error detect standby check sr.4 l&at block lock-bit error i srs,sr.4,sr.3 and sr.l am only cleared by tfw clear status register command in cases where multiple mock lock-bits are set before full stahis is checked. if error 1s d&tad. clear the status register before attempting retry or other error recovery. figure 12. set block lock-bit flowchart rev. 1.9
sharp lhf16ka9 l- stall x wnto 60h i i i c?- 0 sr.7- 4 1 check if desired full status check procedure read status register data(see above) clear block lock-bits successful i command q---q&y writ9 clear blodc data=doh lock-sits confirm addr-x read standby i data&oh add-x chak sr.7 l=wsm ready oiwsm busy write ffh after the clear block lock-sib operation to place device in read array mode. command i standby chedc sr.3 i+,, error detect standby standby check sr.5 l-clear block lock-bits error sr.s,sr.4,sr.3 and sr.1 am only deared by the clear status register command. if error is detected. clear the status register before attempting retry or other ermr mcovely. figure 13. clear block lock-bits flowchart rev. 1.9
lhflgka9 30 -- 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three- line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read#qontrol line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit configuration polling sts is an open drain output that should be connected to vcc y b a pullup resistor to provide a hardware method of detecting block erase, full chip erase, (multi) .word/byte write and block lock-bit configuration completion. in default mode, it transitions low after block erase,, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to v,, when the wsm has finished executing the? internal algorithm. for alternate sts pin configurations, see the configuration command. sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. sts, in default mode, is also high z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a o.luf ceramic capacitor connected between its vcc and gnd and between its v,, and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7uf electrolytic capacitor should be placed at the array?s power supply connection between vcc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 vpp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v,, power supply trace. the v,, pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. use similar trace widths and layout considerations given to the v,, power bus. adequate v,, supply traces and decoupling will decrease v,, voltage spikes and overshoots. rev. 1.9
sharp lhflgka9 31 . - 5.5 vcc, vpp, rp# transitions block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if v,, falls outside of a valid v,,,, range, voo falls outside of a valid vccir range, or rp#=v,,. if v,,x error is detected, status register bit sr.3 is set to ?1? along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v,, during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, sts(if set to ry/by# mode) will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v,, clear the status register. the cui latches commands issued by system software and is not altered by v,, or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power-down or after voc transitions below vlko. after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after v,, transitions down to v,,,,, the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against accidental block and- full chip , erasure, (multi) word/byte writfhg or block lock-bit configuration during power transitions. upon. power-up, the device is indifferent as to which power supply (v,, or vc,) powers-up first. internal circuitry resets the cui tc read array mode at power-up. a system designer must guard against spuriou: writes for voo voltages above vlko when v,, i! active. since both we# and ce# must be low for : command write, driving either to v,, will inhibit writes the cul?s two-step command sequence architecturt provides added level of protection against dat: alteration. in-system block lock and unlock capability prevent: inadvertent data alteration. the device is disablec while rp#=vil regardless of its control inputs state. 5.7 power dissipation when designing portable systems, designers mus consider battery power consumption not only durin! device operation, but also for data retention durin! system idle time. flash memory?s nonvolatiliq increases usable battery life because data is retainec when system power is removed. in addition, deep power-down mode ensure: extremely low power consumption even when systen power is applied. for example, portable computin{ products and other power sensitive applications tha use an array of devices for solid-state storage car consume negligible power by lowering rp# to v,, standby or sleep modes. if access is again needed the devices can be read following the tphqv ant t,,,, wake-up cycles required after rp# is firs raised to v,,. see ac characteristics- read oni) and write operations and figures 17, 18, 19, 20 foi more information. rev. 1.9
shari= - _ - lhfigkas 32 .- 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, erase, write and block lock-bit configuration . . . . . . ..o?c to +70?c(1) temperature under bias . . . . . . . . . . . . . . . -10c to +8o?c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125x voltage on any pin (except voo, v,,) . . . . . . . . . . . . . . . -0.5v to voo+o5v(*) voc suply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +7.ov(*) v,, update voltage during erase, write and block lock-bit configuration . . . . ..-0.2v to +7.ov(*) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . looma *warning: stressing the device beyond th ?absolute maximum ratings? may cause permaner damage. these are stress ratings only. operatio, beyond the ?operating conditions? is nc recommended and extended exposure beyond th, ?operating conditions? may affect device reliability. notes: 1. operating temperature is for commercia temperature product defined by this specification. 2. all specified voltages are with respect to gnd minimum dc voltage is -0sv on input/output pin and -0.2v on vco and v,, pins. durin! transitions, this level may undershoot to -2.ov fo periods <20ns. maximum dc voltage oi input/output pins and vcc is vc,+o.5v which during transitions, may overshoot to voc+2.ov fo periods e20ns. 3. output shorted for no more than one second. nc more than one output shorted at a time. 6.2 operating conditions 6.2.1 capacitan?ce(?) .i? symbol parameter c,n input capacitance cn, ,t output capacitance note: 1. sampled, not 100% tested. t,=+25?c, f=l mhz typ. max. 7 10 9 12 unit condition pf v,,=o.ov pf ?jr-,, ,r=o.ov rev. 1.9
sharp lhf16ka9 6.2.2 ac inputiijtput test conditions i ac test inputs are driven at 3.ov for a logic ?1? and o.ov for a logic ?0.? input timing begins, and output timing en&, at 1.5v. input rise and fall times (10% to 90%) cl0 ns. figure 14. transient input/output reference waveform for vcc=5v~0.25v (high speed testing configuration) ac test inputs are driven at voh (2.4 vm) for a logic ?1? and vol (0.45 vttl) for a logic ?0.? input timing begins at vih (2.0 vm) and vil (0.8 vm). output timing ends at vih and vil. input rise and fall times (10% to 90%) sharp lhflgka9 5.2.3 dc characteristics dc characteristics v(-c=sv test symbol parameter notes typ. max. unit conditions ?ll input load current 1 *l pa vcc=vccmax. v,,=v,c or gnd ?lo output leakage current 1 *lo lja vcc=v&lax. vcllit=vcc or gnd ?cc, vcc standby current 1,396 cmos inputs 25 100 cia v,,=v,,max. ce#=rp#=vcc?0.2v ttl inputs 2 4 ma vcc=vccmax. ce#=rp#=v,, ?cc0 vcc deep power-down ? current 1 15 cia rp#=gnd*o.2v i,,,,(sts)=oma ?ccr vcc read current 1 a6 cmos inputs 50 ma vcc=vccmax. ce#=gnd f=8mhz, lout=oma ttl inputs 65 ma vcc=vccmax., ce#=v,, f=8mhz, 10,,t=oma , b write or set block rev. 1.9
sharp lhflgka9 dc characteristics (continued) votes: i. all currents are in rms unless otherwise noted. typical values at nominal v,, voltage and ta=+25?c. !* ?cc,, and ?cces are specified with the device de-selected. if read or byte written while in erase suspend mode, the device?s current draw is the sum of lccws or lcces and i,,, or i,,,, respectively. 3. includes sts. 1. block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when v#i,,lk, and not guaranteed in the range between v,,lk(max.) and v,,,,(min.) and above vpph,(max.). 5. automatic power savings (aps) reduces typical icc, to 1 ma at 5v vcc in static operation. j. cmos inputs are either vcc+0.2v or gndk0.2v. ttl inputs are either v,, or v,,. 7. sampled, not 100% tested.
shari= lhflgka9 _ - 36 6.2.4 ac chara-iterlstlcs - read-only operations(?) vcc=5v+0.5v, 5vt0.25v, t,po ?c to +7o?c vcc=5v*0.25v) lh28f _ _ _ _ _ . :16os5-l70@) 1 , vcc=5v*o.5v 1 1 lh28f16os5-l80@) ff, n, byte# to output in high z 3 25 30 ns telfl ce# low to byte# high or low tf, fh 3 5 5 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t,lav-blov after the falling edge of ce# without impact on telqv. 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). 5. see transient input/output reference waveform and transient equivalent testing load circuit (high speed configuration) for testing characteristics. 6. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. rev. 1.9
sharp .- lhf16ka9 _ - 37 device address selection data valid 11.1.1111. address stable hi ce#(e) vih oe#(g) ml vh .*1..,,,., we#(w) wl voh data(d/q) vol tphov ?????7 . . note: ce# iddefined as the latter of &,$i and ce# going low or the first of ceo# or ce,# going high. figure 17. ac waveform for read operations rev. 1.9

sharp ., , related docutieni informational document no. ap-00 i-sd-e ap-006~ft-e ap-ootsw-e note : document name flash memoq family so&are drivers data protection method of sharp flash memoq~ rp#, vpp electric potential switching circuit i. lmemational customers should contact their local sharp or distribution sales office.
shari= pfieuminary b 1 ame i tsops6-p-1420 1 le4d finish ! plating note phstic body dimens ions do not include burr 1 *fc ; of resin. dra9fing no. i ml115 1 unit 1 mm 1

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